1. Field of the Invention
The invention relates to the process of designing an integrated circuit. More specifically, the invention relates to a method and an apparatus for using verifying an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip.
2. Description of the Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process generally begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are generally formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photo resist layer coated wafer. (Note that the term xe2x80x9cmaskxe2x80x9d as used in this specification is meant to include the term xe2x80x9cretical.xe2x80x9d) Light is then shone on the mask from a visible light source or an ultraviolet light source.
This light is generally reduced and focused through an optical system that contains a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
A layout for a semiconductor chip is often stored in a standard hierarchical format, such as GDSII stream format. For example, FIGS. 1A, 1B and 1C illustrate how a layout T, can be composed of a sub-instance cell A and a sub-instance cell B, wherein the sub-instance cell A further includes a sub-instance cell C. FIG. 1A illustrates a nodal representation of this hierarchy, while FIG. 1B illustrates a corresponding graphical representation.
FIG. 1C presents a specification of the layout in code form. In this form, the layout, T, includes a reference list. This reference list includes a reference to instance cell A along with an associated transformation, TA, and a reference to instance cell B along with an associated transformation, TB. Similarly, the layout for instance cell A includes geometrical features associated with instance cell A along with a reference instance cell C. This reference to instance cell C is accompanied by a transformation of instance cell C with respect to A, TCA. The layouts for instance cell B and instance cell C include geometrical features associated with instance cell B and instance cell C, respectively.
Representing a layout in a hierarchical format can cause problems for various operations related to production of a semiconductor chip, such as die-to database inspection of a mask, defect analysis on a wafer or a mask, verification of a layout against a simulated silicon image of the layout, and proximity effect correction during mask writing.
During any of these operations, interactions between nodes within the hierarchical representation can cause erroneous results. This problem can be remedied by collapsing the hierarchy down into a single monolithic layout before performing the operations. Unfortunately, this technique can be prohibitively slow because the operations must be applied to the entire layout, even though many of the instance cells in the layout may be repeated.
Therefore, a need arises for a system and method of efficiently processing a layout using a hierarchical representation without the above-describe problems.
Accordingly, the present invention uses IB based representation to rapidly process a transformed layout. Specifically in one embodiment of the present invention a transformed layout, which was generated from a reference layout is verified using an IB based representation that is also generated from the reference layout.
The IB-based representation includes sets of instance cells. In general the sets include a master instance cells and slave instance cells. Although not all sets include slave instance cells. Because in an IB-based representation the slave instances share the same geometries as the master instances all the instances in a set have the same geometry. In general, the generation of the transformed layout is more subject to systemic errors rather than random errors. Thus, if all the instance cells in a set have the same geometry verifying a subset of instance cells provides adequate verification that all the instance cells of the set are generated correctly.
Thus, in accordance with one embodiment of the present invention, a subset of each set of instance cells is selected from the IB based representation. In some embodiments the subset consists of just the master instance cell of the set. In other embodiments the subset includes one or more slave instance cells. In still other embodiments of the present invention the subset includes the master instance cell and one or more slave instance cells. For each instance cell in the subset, the corresponding area of the transformed layout is simulated to generate a simulation image. The simulation image is then compared with the instance cell. For instance cells that are not in the subset, the comparison results can be copied from one of the instance cells within the subset.